Copyright @1995, JEDEC; 2000, IEC JESD22-C101 Page 3 8. MEASUREMENT PROCEDURE 8.1 With the ohmmeter, verify that the resistance of the current sensing resistors in all discharge heads o be used is 1 ± 0.1 2. 8.2 With the use of the standard test modules in 7.1, perform three tests in section 9. For each test. Raise the potential of the standard test module to the voltage indicated in table 3. 1. 2. Discharge the standard test module at least five times at both positive and negative polarities. Note that with the Field-Induced CDM technique, both discharge polarities are obtained on alternate discharges with a single power supply setting. Therefore the power supply voltage may be set to either polarity. The peak currents should have the same magnitude but opposite sign for the two discharge polarities. Record the waveforms using the oscilloscope and take the average values of the parameters specified in table 3. 4. Repeat the step 1 through step 3 for additional discharge heads as needed. If the waveform characteristics do not meet the requirements in table 3, clean the test modules (see 13.5) and repeat step 1 through step 3. If the waveform still can not meet the requirements in table 3, any data obtained since 6. the last verification shall be invalidated and the simulator shall be serviced. 9.WAVEFORM CHARACTERISTICS 6 The waveforms shall appear as shown in figure 2 for the positive polarity and its reverse for the negative polarity. The average values specified in 8.2 shall meet the specifications in table 3: TABLE 3 CDM WAVEFORM CHARACTERISTICS Test Number #1 #2 #3 standard test module Small Small Large test voltage (V) 500 1000 200 peak current magnitude (A) 4.5 ±0.5 9± 1 3.5 ± 0.5 Ip rise time (ps) tr <400 <400 full width at half height (ns) Td 1.0±0.5 1.0±0.5 <50% Ip <50% Ip undershoot (A, max.) u- u+ <25% Ip <25% IP overshoot (A, max.) 10. VOLTAGE LEVELS 10.1 The recommended voltage levels for CDM ESD testing are: 100 V 1000 V 200 V 2000 V 500 V 10.2 To determine the threshold more accurately, it is permitted to test at other voltage levels in addition to those specified above. Test Method C101 Copyright 1995, JEDEC; 2000, IEC JESD22-C101 Page 4 11. TEST PROCEDURE 11.1 The test shall be carried out at room temperature. 11.2 Testing may begin at any convenient voltage level from 10.1. 11.3 Obtain at least three samples which have been verified to meet their data specifications. 11.4 For each component, apply five positive and five negative discharges to each pin. (For Field- induced CDM simulators, a negative pulse automatically follows a positive pulse or vice versa. ) Allow enough time (>2o0 ms) between discharges for the component to reach the full test voltage level. During the test, either watch the oscilloscope connected to the current monitoring resistor to verify that the discharges take place, or verify the scope trigger using software in computer-controlled systems. Apply the CDM stresses to all three components. 11.5 Test each of the components, using the failure criteria of section 12. 11.6 Components that pass the test may be reused at other voltage levels. Components that fail may not be used in tests at other levels. It is permitted to use new components for every voltage level. That is, step-stressing is not required. 11.7 The component code passes a voltage level if all three samples stressed at this level pass. The component code fails at the voltage level if one or more samples fail at this level. 11.8 The CDM WITHSTAND THRESHOLD of the COMPONENT CODE is the highest level for which three out of three stressed samples pass. If the component code does not pass any level, its threshold is O V. (Note: For the threshold level only, the rule for zero failures out of three samples is relaxed to allow one failure out of six samples or two failures out of twelve samples, etc. However, no sample failure shall occur at any test voltage level lower than the withstand threshold.) For example, if five out of six