IEC IEC 60191-6-12 Edition 2.0 2011-06 INTERNATIONAL STANDARD NORME INTERNATIONALE colour inside Mechanical standardization of semiconductor devices- Part 6-12: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guidelines for fine-pitch land grid array (FLGA) Normalisationmecaniquedesdispositifsasemiconducteurs Partie6-12:Regles generales pour lapreparation des dessins d'encombrement desboitiersdesdispositifsasemiconducteursamontageensurface-Lignes directrices de conception pour les boitiers matriciels a plots et a pas fins (FLGA) I materiall THIS PUBLICATION IS COPYRIGHTPROTECTED Copyright2011 IEC, Geneva, Switzerland Allrights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microflm, without permission in writing from either IEC or IEC's member National Committee in the country of the requester. If you have any questions about IEC copyright or have an enquiry about obtaining additional rights to this publication, please contact the address below or your local IEC member National Committee for further information. Droits de reproduction réserves. Sauf indication contraire, aucune partie de cette publication ne peut etre reproduite et les microfilms, sans Faccord ecrit de la CEI ou du Comite national de la CEI du pays du demandeur. Reuters Si vous avez des questions sur le copyright de la CElou si vous desirez obtenir des droits supplementaires sur cette publication, utilisez les coordonnees ci-apres ou contactez le Comite national de la CEl de votre pays de residence. (Scientific), Inc., IEC Central Office 3, rue de Varembe CH-1211 Geneva 20 Switzerland Email: inmail@iec.ch Web: www.iec.ch About the IEC International Standards for all electrical, electronic and related technologies. AboutIEC publications The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the latest edition, a corrigenda or an amendment might have been published. - Catalogue of IEC publications: www.iec.ch/searchpub It also gives information on projects, withdrawn and replaced publications. - IEC Just Published: www.iec.ch/online news/justpub Stay up to date on all new IEC publications. Just Published details twice a month all new publications released. Available on-line and also by email. - Electropedia: www.electropedia.org The world's leading online dictionary of electronic and electrical terms containing more than 20 000 terms and definitions in English and French, with equivalent terms in additional languages. Also known as the International Electrotechnical Vocabulary online. - Customer Service Centre: www.iec.ch/webstore/custserv If you wish to give us your feedback on this publication or need further assistance, please visit the Customer Service Centre FAQ or contact us: Email: csc@iec.ch Tel.: +41 22 919 02 11 Fax: +41 22 919 03 00 A propos de la CEI La Commission Electrotechnique Internationale (CEl) est la premiere organisation mondiale qui élabore et publie des AproposdespublicationsCEl Le contenu technique des publications de la CEl est constamment revu. Veuillez vous assurer que vous possedez I'edition la plus récente, un corrigendum ou amendement peut avoir éte publie. - Catalogue des publications de la CEl: www.iec.ch/searchpub/cur fut-f.htm Le Catalogue en-ligne de la CEl vous permet d'effectuer des recherches en utilisant differents criteres (numero de reference, texte, comite d'etudes,...). Il donne aussi des informations sur les projets et les publications retirees ou remplacees Just Published CEl: www.iec.ch/online news/justpub Restez informe sur les nouvelles publications de la cEi. Just Published detalle deux fois par mois les nouvelles I or distribution is permitted. publications parues. Disponible en-ligne et aussi par email. - Electropedia: www.electropedia.org Le premier dictionnai
IEC 60191-6-12 2011 Mechanical standardization of semiconductor devices - Part 6-12 General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guid
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